The following is a list of relevant technical papers along with comments re each paper. These papers relate to DRL and the wireless mobile application.

These three papers are historical descriptions of how coarse-grained DRL may be most effectively used.

1. Rabaey, Jan M. "Reconfigurable Processing: The Solution to Low-Power Programmable DSP." This is a 1997 IEEE paper that discusses granularity in DRL and relates it to optimum performance (computational power and energy efficiency) in the DSP application. It ties together the block reconfigurable aspects of logic to the granularity of the application algorithms in a given domain. To our knowledge, this is the grandfather paper from a very highly respected academic.
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2. Abnous & Rabaey, "Ultra-Low-Power Domain-Specific Multimedia Processors." This is a 1997 paper written by one of Rabaey's graduate students, tying DRL to domain-specific applications. Gives a good bit more detail than paper No. 1.
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3. Abnous, Arthur, et al, "Evaluation of a Low-Power Reconfigurable DSP Architecture." This is a multi-author paper in which comparisons between a reconfigurable architecture and other logic implementation techniques are quantitatively presented.
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These four papers are sequentially improved descriptions of how DRL may be used to best meet the needs of high-performance baseband and application processors in 3G and beyond mobile phones.

4. Alsolaim, et al, "Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems." (0-7695-0871-5/00 $10.00 @ 2000 IEEE). This is a relatively early paper describing the benefits of DRL in future wireless mobile applications.
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5. Rabaey, Jan M. "Silicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play?" [R.W. Hartenstein and H. Gruenbacher (Eds.): FPL 2000, LNCS 1896, pp. 277-285,2000. Springer-Verlag Berlin Heidelberg 2000]. This paper gives an overview of how the important benefits of DRL line up very well with the needs of future wireless mobile handset baseband and application processors.
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6. Smit, Gerard, et al, "Dynamic Reconfiguration in Mobile Systems." [M. Glesner, P. Zipf, and M. Removell (Eds.): FPL 2002 LNCS 2438, pp. 171-181, 2002, Springer-Verlag Berlin Heidelberg 2002.] This is a more recent paper that ties domain-specific DRL technology to the mobile wireless application and speaks to the use of both fine- and coarse-grained DRL.
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7. Swaminathan, Sriram, et al, "A Dynamically Reconfigurable Adaptive Viterbi Decoder." (FPGA '02, February 24-26, 2002, Monterey, CA). This is a rather specific paper relating the use of DRL to the processing of the CDMA Viterbi algorithm in a "modified" format.
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8. Smit, Gerard, et al, "Reconfigurable Mobile Multimedia Systems." University of Twente, Departments of Computer Science and Electrical Engineering. An introductory summary of Havinga's PhD thesis.
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These papers relate to the Context APA and the synergistic benefits it provides to the DRL logic architecture.

1. Robertson, James E., "A New Class of Digital Division Methods," IRE Transactions on Electronic Computers, Vol. EC-7, no. 3, pp. 218-222, September 1958. A grandfather paper describing a recursive technique best applied with floating-point arithmetic.

2. Volder, Jack E., "The CORDIC Trigonometric Computing Technique," IRE Transactions on Electronic Computers, Vol. EC--8, pp. 330-334, September 1959. An early paper describing conversions between binary and mixed radix number systems.

3. Trivedi, Kishor S. and Ercegovac, Milos D., "On-line Algorithms for Division and Multiplication," IEEE Transaction on Computers, Vol. C-26, No. 7, pp. 681-687, July 1977. An early paper describing online (Most Significant Digit First) algorithms for division and multiplication and the benefits thereof.

4. Trivedi, Kishor S. and Rusnak, Joseph G., "HIGHER RADIX ON-LINE DIVISION," Proceedings of Fourth Symposium on Computer Arithmetic, Santa Monica, CA, , pp. 164-174, Oct. 1978. A more formalized, mathematically correct derivation of a higher radix online division algorithm.

5. Koren, Israel, "Computer Arithmetic Algorithms," Prentiss-Hall, 1993, pp. 127-150. A contemporary description of the SRT/MSDF fast division algorithm, its implementation and benefits.

6. Bondalapati, Kiran, et al, "Dynamic Precision Management for Loop Computations on Reconfigurable Architectures." This is a paper given at the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines in 1999. This paper quantifies in a general way the benefits of one aspect of our APA, i.e. variable calculational precision.
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