Our multiprocessor DRL is highly scalable from a minimum of 4 to a maximum of 128 processors. Each application will have a unique configuration, determined to provide the best performance within an implementation that meets all of the constraints of that particular application.

Every communication algorithm has a particular, often unique, structure in the sense of the number of nodes, the data word bit-width, the dataflow characteristics and the resolution; the signal processing performance data derived therefrom are obviously affected by that structure. We have run many different communication algorithms on our software simulator and compiled resultant performance data sets, including execution times (E.T.), power consumptions (P.C.) and code densities. Recognizing that each of these performance data sets are uniquely related to the given algorithm structure, we have nevertheless selected representative examples to provide the data given in the table below. Where practical, the software simulator-determined performance data were confirmed by scaling experimental data from our emulator.

The algorithms selected were mapped in their original or "unmodified" C-code. All of these algorithms may be (and many already have been!) modified/optimized such that the signal processing performance of our DRL will be substantially improved. Performance improvement factors of between two and four have been analytically confirmed when such modifications are made.

A single Context DRL baseband chipset can support 512 full duplex, multiple CODEC VoIP channels with 128 msec echo cancellation tail.

For wireless basestation, SDR and 802.11 application performance data - stay tuned…